The present invention is directed to a method for the implementation of function tests at individual semiconductor circuit levels that are provided for vertical integration.
Semiconductor circuits are currently manufactured in planar technology. The complexity that can be achieved on a chip is limited by its size and by the structural fineness that can be achieved. The performance capability of a system composed of a plurality of interconnected semiconductor chips is significantly limited in conventional technology by the limited number of possible connections between individual chips via terminal contacts (pads), by the low speed of the signal transmission between different chips via such connections (interface circuits pad/printed circuit board), by the limited speed due to highly branched interconnects given complex chips, and by the high power consumption of the interface circuits.
These limitations in the use of planar technology can be overcome with three-dimensional circuit techniques. The arrangement of the function levels above one another allows parallel communication of these components with little outlay for electrically conductive connections in one level. Speed-limiting interchip connections are also avoided. Despite enhanced functionality, such a vertically integrated chip can also be accommodated in the same housing.
In order to avoid losses in the yield of functional chips, it is necessary that only circuit levels that have been tested and found fully functional are connected to one another. This is unproblematical as long as the circuit levels are a matter of, , i.e. of independently functioning circuits. Given such circuits, it is possible to test them on the wafer on which they are manufactured before they are separated from one another and mounted in housings. When, however, the individual circuit level only functions in interaction with the neighboring levels that are to be vertically arranged, when contacting with a probe is not possible on the wafer due to a lack of contact locations, then testing is only possible without further measures after an assembly of the circuit levels which, however, is irreversible. The yield, is then drastically reduced.
The circuits are usually contacted for testing by placing fine test probes onto the bond pads. The pads, however, have substantially larger dimensions than the connection contacts of the circuit levels provided for vertical integration. Moreover, the number of contacts is thereby, substantially greater (approximately 10,000-100,000). The fine dimensions and the high number of contact locations preclude the employment of standard test probes. Another testing method utilizes electron-optical methods. This, however, requires circuit levels, a requirement that is not satisfied here. The voltage supply is not yet assured, particularly given insulated circuit levels.